![Photo of research loading a snall chip into the reactive ion etcher (RIE) at the nanopatterning Cleanroom in the Stanford Nano Shared Facilities.](https://cars.stanford.edu/files/styles/webinar_image_size/public/l1000183.jpg)
Stanford’s membership in a new national consortium, the National Semiconductor Technology Center (NSTC) will aid researchers in developing the next generation of chips essential for electronics, says electrical engineer H.-S. Philip Wong.
Stanford’s membership in a new national consortium, the National Semiconductor Technology Center (NSTC) will aid researchers in developing the next generation of chips essential for electronics, says electrical engineer H.-S. Philip Wong.